When a metal-oxide-semiconductor field-effect transistors (MOSFETs) is scaled down through various technology nodes, high k dielectric materials and metals are adopted for gate dielectric and gate electrode, respectively, to form a gate stack. However, the gate dielectric scaling has little improvement to the device speed because of various parasitic capacitances associated with the gate stack. By the conventional process and the structure formed thereby, the parasitic capacitance between the contact and the gate stack, and the parasitic capacitance between the gate stack and the substrate cannot be effectively reduced. Additionally, other possible issues associated with the conventional method include gate filling and silicon recess.